//****************************************************************
// File Name  : count.v
// Author     : guangzu.he
// Date       :
// Description:
//
//****************************************************************
`timescale 1ns/1ns

module my_count(
        input   wire            clk,
        input   wire            rst_n,
        output  reg [15:0]          q
        );

reg  d1 /* synthesis keep */;
reg  d2 /* synthesis keep */;
reg  d3 /* synthesis keep */;
always@(*)begin
    d2 <= ~d1;
    d3 <= ~d2;
    d1 <= ~d3;
end


reg q1,q2;

always@(posedge clk or negedge rst_n)
if(!rst_n)begin
    q1 <= 0;
    q2 <= 0;
end
else begin
    q1 <= d3;
    q2 <= q1;
end

always@(posedge clk  or negedge rst_n)
    if(!rst_n)
        q <= 0;
    else
        q <= q + q2;

endmodule